February 15, 2003

Exponential or explosive — neither word is strong enough for the meteoric ascent of semiconductor technology ever since Jack Kilby of Texas Instruments built the legendary first IC forty years ago. In those pioneering days, ICs displayed a handful of transistors klutzy enough to be seen by the naked eye.

Now the industry is on the brink of logic ICs crammed with over 100 million transistors, whose critical dimensions are far shorter than the wavelength of visible light. Driving the advance has been a horde of scientists and engineers from many disciplines, chiseling away at the boundaries of semiconductor science.

For all its seeming precision, the 100-million-transistor IC is a fuzzy milestone at best. Dynamic RAMs, which now boast more than a billion transistors, passed it years ago. According to Semiconductor Industry Association (SIA) San Jose California 1998 roadmap update, microprocessors will contain 76 million transistors apiece in 2002 and 200 million apiece by 2005. The ICs of these generations will be built with 130- and 100-nm technologies, respectively.

The steady downscaling of CMOS device dimensions has been the main stimulus to the growth of microelectronics and the computer industry over the past two decades. The more an IC is scaled, the higher becomes its packing density, the higher its circuit speed, and the lower its power dissipation. Today, after many generations of scaling, the smallest feature in a CMOS transistor is approaching atomic dimensions and off-state leakage current per transistor has been rising because thermal energy does not scale. So how much longer can CMOS scaling continue.

As the integration level of ICs moves toward 100 million transistors in the next few years, key issues of transistor design must be reexamined for 0.10-0.13mm generation technology.

In previous CMOS generations, it was possible to disregard many parasitic components like off-state leakage and gate current. But in the not-so-distant future, these undesirables will grow rapidly as the fundamental limits imposed by thermodynamics and quantum mechanics close in on the technology. Fortunately, the margins in today’s devices will be enough to blunt the impact of such effects for perhaps a few generations. All the same, extracting the most performance while extending the limit of CMOS will require several elaborate schemes, including multiple threshold voltages, optimum two-dimensional nonuniform doping, and near atomic level control of gate oxide thickness and source-drain profile.

For transistors built between the year 2003 and 2006 in the 0.10-0.13mm lithography generation, minimum channel length will be 0.05mm, yielding a current gain frequency well beyond 100GHz and an unloaded digital circuit delay of about 10ps. For a chip with an integration level of 100 million transistors, the average leakage current of turned-off devices-that is, the sub-threshold current at zero gate voltage- should not exceed a few tens of nanoamperes. This constraint restricts the threshold voltage to a minimum of about 0.2V at the operating temperature, which can be 100oC in the worst case. Another key challenge for process technology in the 0.10-0.13mm generation is to produce source and drain junctions with truly abrupt lateral doping profiles. The abruptness needed is on the scale of a fraction of the channel length a decade of change in doping concentration within a distance on the order of 10nm or less. Otherwise, short-channel effects degrade rapidly. The reason is that channel length is largely set by the points where current is injected from the surface inversion layer into the bulk silicon, namely, inside the source and drain regions at a doping concentration of 1019cm-3 typically. Any source-drain doping that extends beyond this point into the channel creates a problem, in that it tends to compensate or counter-dope the channel region and so to aggravate the short channel effect. Abrupt lateral profiles also allow the gate-to-source and gate-to-drain overlaps to scale down with the channel length for improved performance.

To preserve the abruptness of both the source-drain and the halo doping profiles, thermal cycles after the implants must be kept to an absolute minimum. This means ultra-rapid annealing, since the peak temperature must be kept high to activate the dopants at a concentration near the solubility limit. Note that a raised source-drain structure (created, for example, by selective epitaxial growth) does not by itself satisfy the abruptness requirement, whatever its merits in helping to make contacts and reduce the effective junction depths.

By the year 2005, scaling IC supply voltages down below 1 volt will result in at least 10 of today’s microprocessors fitting onto a single chip. To designers of Very Large Scale Integration electronics chips (VLSI). circuits, this is an exciting, but daunting, prospect. Delivering that enormous device volume offers tremendous opportunities — both to enhance functional power dramatically and to fail in a truly career-threatening fashion. How the effort will turn out will depend, to a large degree, on how carefully five key issues are considered, namely, switching currents, optimization, asynchronization, reuse, and design skills. In any discussion of them, certain subjects — interconnections, for example, will prove to cut across all five topics. All the same, the issues offer a useful view on what designers will face in handling these complexities.

In examining the VLSI design problem, it is useful to focus primarily on microprocessor design. All of the chip design problems — interconnect complexity, many kinds of storage and logic circuits, performance, and productivity — are particularly stressed by this application. It highlights the same issues as are found in more application-specific design areas, such as digital signal processing, and in more general-purpose products, such as logic arrays and static RAMs (Table 1). As will become apparent, even challenges such as design re-use, which were previously not very important in microprocessor design, will play a big role in meeting the microprocessor performance expectations if 2005.

According to the International Technology Roadmap for Semiconductors , potential parameters of the VLSI technology of 2005 include increases in density, speed, and power (Table 2). They imply increased requirements for the art of design — particularly for handling rapidly changing currents, optimization, asynchronization, reuse, and managing design skills.

The most prominent of PC microprocessor parameters is the clock frequency, or “the megahertz of the processor”. Pushing it above 1GHz will require not just a simple scaling of the devices to smaller sizes but material, process, and design changes as well.

In one tick of the processor clock, the data ripples through, a series of logic gates between registers, and covers a respectable distance across the face of the IC. (A logic depth of 12 gates was assumed in the accompanying figures). In the past decade, shrinking line-width down to the present 250 nm has steadily shrunk both transistor gate delay and on-chip interconnect delay between gates, since the logic gates are closer together. As a direct consequence of this scaling, microprocessors are speeding up. Beyond 250nm, however, is a realm where the interconnect percentage of the delay, associated with sending the signals on ever narrower wires between the switching transistors, may reverse itself. Instead of the percentage decreasing with technology line-width, the interconnect delay percentage will start to increase with line-width reduction. As the interconnect shrinks to 100 nm, its increasing delay begins to dominate the overall gate delay. This delay depends on the time constant of the interconnect.

The writer is a Fulbright Fellow and professor at the Department of Electronic and & Telecommunication Engineering, Mehran University of Engineering & Technology, Jamshoro

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