August 24, 2002

INTEL, Aug 15, unveiled several technology breakthroughs that the company has integrated into its new 90-nanometer (nm) process, the most advanced semiconductor manufacturing process in the industry.

This new 90 nm (a nanometer is one-billionth of a meter) process combines higher-performance, lower-power transistors, strained silicon, high-speed copper interconnects and a new low-k dielectric material. This is the first time all of these technologies will be integrated into a single manufacturing process.

“While some are slowly transitioning production to 130 nm (0.13 micron) process on 200 mm wafers, we are moving ahead with the most advanced 90 nm technology exclusively on 300 mm wafers,” said Dr Sunlin Chou, senior vice president and general manager of Intel. “This combination will allow Intel to make better products and reduce manufacturing costs.”

For more than a decade, Intel has been driving the pace of Moore’s Law by introducing a new process generation every two years. The 90 nm process is the next generation after the 0.13 micron process, which Intel is using today to make the bulk of its microprocessors.

Intel’s new 90 nm process will feature transistors measuring only 50 nm in length (gate length), which will be the smallest, highest performing CMOS transistors in production. By comparison, the most advanced transistors in production today, found in Pentium 4 processors, measure 60 nm. Small, fast transistors are the building blocks for very fast processors. These transistors feature gate oxides that are only five atomic layers thick (1.2 nm). A thin gate oxide increases transistor speed. Intel has integrated its own implementation of high-performance strained silicon into this process. By using strained silicon, current flows more smoothly, increasing the speed of the transistors. This will be the first process in the industry to implement strained silicon in production.

The process also integrates a new carbon-doped oxide (CDO) dielectric material that increases signal speed inside the chip and reduces chip power consumption. This dielectric is implemented in a simple, two-layer stack design, which is easy to manufacture.

In Feb, Intel used its 90 nm process to make the world’s highest capacity SRAM chips at 52 megabits (capable of storing 52 million individual bits of information). These fully functional chips pack 330 million transistors in an area measuring only 109 square millimeters -about the size of a fingernail.

These chips also implement an industry-leading SRAM cell size, measuring only one square micron — a milestone long coveted by silicon designers and manufacturers. By comparison, a red blood cell is about 100 times larger. Small SRAM cells allow for the integration of larger data caches in processors, which increase performance. These semiconductor devices were manufactured at Intel’s 300 mm development fab (called D1C) in Hillsboro, Oregon, where the process was developed.

“Intel’s 90 nm process is very healthy today and we are routinely producing these wafers and chips in our development fab,” said Mark Bohr, Intel Fellow and director of process architecture and integration. “By next year, we will be the first company to have a 90 nm process in volume manufacturing.”

Intel’s 90 nm process also integrates seven layers of high-speed copper interconnects, which increase processor performance. A combination of 248 nm and 193 nm wavelength lithography equipment is used for this process. The company also expects to reuse about 75 per cent of the process tools used on its current 300 mm version of its 0.13 micron process, lowering implementation costs and ensuring a mature tool set for the manufacturing ramp. The 90 nm process will be ramped into high volume in D1C and transferred to other 300 mm manufacturing fabs starting next year.